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Comparative study of InP/InGaAs double heterojunction bipolar transistors with InGaAsP pacer at base-collector junction
Tsai Jung-Hui1, Lee Ching-Sung2, Jhou Jia-Cing1, Wu You-Ren1, Chiang Chung-Cheng1, Chao Yi-Ting1, Liu Wen-Chau3
1Department of Electronic Engineering, National Kaohsiung Normal University, 116, Kaohsiung 802, Taiwan
2Department of Electronic Engineering, Feng Chia University, 100, Taichung 407, Taiwan
3Department of Electrical Engineering, National Cheng Kung University, 1, Tainan 701, Taiwan
Поступила в редакцию: 14 марта 2013 г.
Выставление онлайн: 19 сентября 2013 г.

In this article, the influence of InGaAsP spacers inserted at base-collector (B-C) junction in the InP/In0.53Ga0.47As double heterojunction bipolar transistors is demonstrated by two-dimensional semiconductor simulation. Due to the addition of an InGaAsP spacer layer, two small potential spikes are formed at B-C junction and the current blocking effect is reduced. The results exhibit that the maximum current gain increases from 30 to 374 (375) as the thickness of InGaAsP spacer layer varies from 0 to 100 Angstrem (300 Angstrem). On the other hand, the device with a thicker spacer layer (300 Angstrem) could effectively improve the knee effect of the current-voltage curves as compared the other devices. In addition, the collector-emitter offset voltages less than 10 mV are observed in the three devices.
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