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Installation for testing avalanche breakdown of field effect transistors operating on an inductive load
Bogdanov A. A.
1, Lyublinskiy A. G.
1, Mikhailov E. M.
1, Tuboltsev Yu. V.
1
1Ioffe Institute, St. Petersburg, Russia
Email: Alexander.A.Bogdanov@mail.ioffe.ru, Alexander.Lyublinsky@mail.ioffe.ru, mikhaylovevgeniyftf@gmail.com, tuboltsev46@mail.ru
The physical processes in field-effect transistors during avalanche breakdown, including those leading to their destruction, are considered. The dominant is thermal mechanism of destruction which occurs when the temperature of the crystal lattice exceeds the intrinsic temperature of the semiconductor. A method for calculating the peak temperature of the lattice during avalanche breakdown is proposed, which makes it possible to estimate the threshold energy of avalanche breakdown above which the transistor collapses. An installation for testing field-effect transistors at avalanche breakdown energies from 0.5 mJ to 2.5 J has been developed. The installation makes it possible to determine the mechanism of destruction, and the suggested circuit design allows to test both field-effect transistors in a package and chips on uncut semiconductor wafers. Keywords: Avalanche breakdown, MOSFET and IGBT transistors, thermal destruction of semiconductor devices, testing equipment.
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